This invention relates to an art for simulation using in the process for developing a computer program and, more particularly, to an art for accelerating simulation processing.
Conventionally, in the process for developing a computer program, a simulation system has been employed for the purpose of correcting detected logic errors on the program and inconformity to the outer conditions by simulating the computer programming. The prior art simulation system is described referring to FIG. 5 to FIG. 7. FIG. 5 shows a simulation procedure as the prior art. FIG. 6 is a block diagram of the simulation system as the prior art. FIG. 7 is a flow chart showing a series of operations of the prior art simulation system.
As FIG. 5 shows, in the conventional simulation procedure, one instruction written in machine language is simulated. After simulating the instruction, a peripheral processing program such as timer/serial is simulated for the number of clocks taken for simulating one instruction written in machine language. These operations are executed each one instruction written in machine language one by one. And also at the end of simulating the peripheral processing program, the interruption processing is executed. In FIG. 5, 7 instructions are simulating. This simulation is so set that an interruption occurs during execution of the instruction 4. Then four instructions are simulated as the interruption instruction.
In FIG. 5, the peripheral processing program is simulated after simulated an instruction 1. Then the peripheral processing program is simulated after simulating an instruction 2. The peripheral processing program is simulated after simulating an instruction 3. The peripheral processing program is further simulated after simulating an instruction 4. The interruption occurs during simulation of the instruction 4. Then the interruption is processed as well as simulating a series of interruption processing instructions.
After simulating the interruption processing instruction 1, the peripheral processing program is simulated. Then, after simulating the interruption processing instruction 2, the peripheral processing program is simulated. After simulating the interruption processing instruction 3, the peripheral processing program is simulated. Then after simulating the interruption processing instruction 4, the peripheral processing program is further simulated. Since the interruption processing instruction 4 represents an end instruction to terminate the interruption, the interruption processing is terminated and the program returns to the step of simulating instructions. After simulating the instruction 5, the peripheral processing program is simulated. After simulating the instruction 6, the peripheral processing program is simulated. After simulating the instruction 7, the peripheral processing program is simulated.
FIG. 6 shows a simulation system for realizing the above described conventional simulation method. FIG. 7 is a flow chart showing a series of operations of the system.
Referring to FIG. 7, an instruction analysis processing step (S1) analyzes the instruction read from an instruction input section 12, shown in FIG. 6, with an instruction analysis section 13. An instruction execution processing step (S2) simulates the instruction with an instruction execution section 14. At a processing step (S5) for judging whether the instruction indicates the end of interruption, when the instruction indicates the end of interruption, the program proceeds to a PSW/PC return processing step (S6). At the PSW/PC return processing step (S6), values of both PSW (Program Status Word) and PC (Program Counter) of a PSW/PC section 18 are returned from the stack. When it is determined that the instruction does not indicate the end of interruption, the program proceeds to a PC update processing step (S7) where the value of the PC of the PSW/PC section 18 is passed. Then a peripheral simulation processing step (S9) simulates a peripheral processing program with a peripheral simulation section 16. At the end of simulating the peripheral processing program, the program proceeds to an interruption control processing step (S11) where interruption is controlled with an interruption processing section 17. At a processing step (S12) for judging whether the interruption occurs, when the interruption occurs, the program proceeds to a PSW/PC return processing step (S13). At this step (S13), values of the P,SW and PC of the PSW/PC section 18 are stacked. Then at. an interruption vector processing step (S14), an interruption vector value is set in the PC. When it is determined that no interruption has occurred, the program returns to the instruction analysis processing step (S1) and repeats simulating the instruction. As aforementioned, the conventional simulation procedure and simulation system simulates the peripheral processing program at every execution of one instruction.
The conventional simulation procedure and simulation system calls the peripheral simulation section at every instruction written in machine language. As a result, the time for calling(accessing) of the peripheral simulation section reflects on a prolonged time for simulation.